Processors having symbolic processing and self-testing capability for a given language are known. This invention is programmable to accept and process any one of the known languages. This flexibility is provided by an instruction decoder with variable instruction set and variable field definition.
Features of symbolic processing include:
1. Bit-wise tag decoding. Essentially the tag contents are determined by sequentially testing one bit of the tag at a time in bit-wise decoding. Improved operation is achieved in this invention by testing large groups of bits at a time.
2. Small tag size. It is generally known to keep the number of bits used to formulate a tag's contents as a small number, say four bits/tag. Improved operation is achieved in this invention by using a higher number of bits/tag.
3. Small microcode stack. Typically a stack memory is limited to a depth of about four to eight words. A microcode sequence includes microinstructions, the solution of which takes several steps. The steps taken require a return to the previous set of microinstructions. The prior art stored information regarding the return in main memory since the number of returns stored may be large. This invention, in comparison, comprises a vast internal memory stack for storing information regarding the return. This return-storage feature reduces the number of memory accesses and thus provides enhanced processor speed.
4. Fixed instruction set. Most processing is accomplished through a hard-wired decoding of a predetermined instruction set. For example, an operation of any given macroinstruction was determined by a given field in an instruction. Thus, for example, a fixed field would define whether an operand was in a memory or a register A hard-wired retrieval was executed to the appropriate memory or register element. This invention demonstrates improved flexibility by employing a variable instruction set.
5. Quantity of registers. A small number of registers from zero to about thirty-two is used in the prior art. Conventional processors use data caching to decrease net memory access time. This invention employs a large number of registers which it uses as a data cache, and therefor involves less memory access time with improved processing speed. In addition, a means of quickly accessing sequential registers is incorporated.
6. Stack manipulation. Typical processors of the prior art were limited to a single stack or hold stack pointers in a standard register. This invention includes five special purpose pointers to handle stacks. Each pointer can be incremented, decremented or loaded independent of other processing. In addition, each pointer can be compared to its limit while it is used to access memory.
7. Control memory. Most control memories do not have the capability of being self tested. Typically the control memory may include 64K by 64-bit words each of which requires a bit by bit verification. It is common in such prior art to use a macro level test. For example to test all of the microcontrol words in a macro level function such as "Add" requires a bit by bit testing of numerous words each 64-bits long. Testing all of the various binary combinations take an exceeding long time. Moreover exhaustive testing is almost impossible to accomplish, since one must test, not only the expected, but the unexpected as well. Such testing of the prior art is costly, inefficient and slow.